#rm *.init
#ln -s ../build/sim/gateware/sim_mem_1.init sim_mem_1.init
#ln -s ../build/sim/gateware/sim_mem_2.init sim_mem_2.init
#ln -s ../build/sim/gateware/sim_mem_3.init sim_mem_3.init
#ln -s ../build/sim/gateware/sim_mem_4.init sim_mem_4.init
#ln -s ../build/sim/gateware/sim_mem_5.init sim_mem_5.init
#ln -s ../build/sim/gateware/sim_mem_6.init sim_mem_6.init
#ln -s ../build/sim/gateware/sim_mem_7.init sim_mem_7.init
#ln -s ../build/sim/gateware/sim_mem.init sim_mem.init
#ln -s ../build/sim/gateware/sim_rom.init sim_rom.init
#ln -s ../build/sim/gateware/sim_sram.init sim_sram.init

rm -f simvvp

iverilog -o simvvp -c bench.vf -D WAVES -D SYNTHESIS -I ../build/sim/gateware/

vvp simvvp

vcd2fst -v wave.vcd -f wave.fst
rm -f wave.vcd
gtkwave -a save.gtkw wave.fst &

